1. Field of the Invention
The present invention relates, generally, to systems and processes for tracking the timing of asynchronous systems in a manner that accommodates timing irregularities in a reference system while maintaining a stable output in a tracking system, and in particular embodiments, to methods for tracking the read timing of a video encoder to the write timing of a video decoder, and systems incorporating the same.
2. Description of Related Art
It is often desirable to transfer data between two or more systems that are not synchronized to a common timing source. For example, in video signal processing systems, video data from a video source such as a video cassette recorder (VCR:) may be transferred to a video display device for viewing. Because the VCR and the video display device do not have a common timing source, the timing between these two asynchronous systems must be carefully controlled, or tracked, to minimize data transfer errors. For purposes of illustration, the timing of a video signal processing system will be discussed in detail below, but it should be understood that the basic timing issues inherent in a video signal processing system are equally applicable to other asynchronous systems.
Modern video signal processing systems often combine audio, video, and graphics for viewing on a video display device. In such multi-media systems, graphics information must be integrated into the audio and video information present within an analog video signal. Integrating graphics information into a video signal is often more easily accomplished in the digital domain. Thus, it is desirable to decode the analog video signal into digital form, integrate the graphics information, and encode the combined signal back into an analog form compatible with typical video display devices.
There are several different standardized formats for the analog video signal. One such format is NTSC (National Television System Committee), which is used in the United States and Japan. Another is PAL (Phase Alternation Lines), which is used in Great Britain and Europe. A third is SECAM, which is used in France, Russia and other parts of Europe. For purposes of simplifying the following description, only NTSC timing will be discussed. However, the other formats are similar and have only slight variations, and therefore the following discussion is conceptually applicable to all formats.
As shown in FIG. 1, within an analog video signal is a single xe2x80x9clinexe2x80x9d 10 of analog video information. A line 10 is typically comprised of a front porch 12, a horizontal synchronization pulse (Hsync) 14, a subcarrier burst 16, and serial pixel data 18.
Subcarrier burst 16 is a sample of the reference subcarrier used to modulate U and V color signals and generate chrominance signals within serial pixel data 18. The U color signal is modulated with one phase of the reference subcarrier, while the V color signal is modulated with a 90xc2x0 phase-shifted version of the reference subcarrier. The U and V color signals are added together to form the chrominance portion of the video signal. When decoding the analog video signal, the reference subcarrier is re-created by phase-locking a frequency source (at the subcarrier burst rate) to subcarrier burst 16. The re-created reference subcarrier is then used to demodulate the chrominance signals within serial pixel data 18 and recover the U and V color signals. In the NTSC standard, the reference subcarrier is defined to have a frequency of 3.579545 MHzxc2x110 Hz, with 227.5 reference subcarrier cycles per line. The line frequency in NTSC is therefore equal to approximately 3.579545 MHz÷227.5 cycles per line, or approximately 15.734 kHz.
Pixel data 18 contains information representing one horizontal line of pixels on a video display device. Serial pixel data 18 is followed by a second Hsync 14, signifying the end of the present line and the start of a new line. Thus, Hsyncs 14 mark the boundary between successive lines 10 of analog video information. The voltage swing of the typical analog video signal is approximately 1.3 volts maximum.
One xe2x80x9cfieldxe2x80x9d of video information is defined as a sequence of lines representing one refresh of a video display device from top to bottom. A vertical synchronization pulse (Vsync) marks the boundary between successive fields of video information. For NTSC, there are 262.5 lines from one Vsync to the next. Thus, the field frequency is approximately 15.734 kHz÷262.5, or approximately 59.94 Hz. As illustrated in FIG. 2, Vsync 20 is not a single pulse, but rather is a signal superimposed on the analog video signal comprised of a series of equalization pulses 22, each pulse being approximately one-half of a line long, followed by a series of wider serration pulses 24, followed by another series of equalization pulses 22. The actual vertical synchronization event 26 occurs at the boundary between the first set of equalization pulses 22 and the sequence of serration pulses 24. Vsync 20 represents the start of a vertical blanking region (Vblanking) 28, the time during which the electron beam in tube-type video display devices resets from the bottom to the top of the display device. Vblanking 28 includes Vsync 20 and 11 more lines of Hsync, that follow Vsync (see reference character 30; FIG. 2 not drawn to scale). At the end of Vblanking 28, an Hsync 14 marks the beginning of the first active line in the new field.
Other timing signals derived from the analog video signal are generated within a typical video signal processing system, including a horizontal active signal (Hactive) and a vertical active signal (Vactive). Referring to FIG. 1, when Hactive 32 is asserted (high in the example of FIG. 1), serial pixel data 18 is being communicated in an active region 34 of a line 10 of analog video information. Associated with Hactive 32 is horizontal blanking region (Hblanking) 38, which occurs when serial pixel data 18 is not being communicated in the active region of a line 10 (i.e., when Hactive 32 is not asserted). Referring to FIG. 2, when Vactive 36 is asserted (high in the example of FIG. 2) a field of video information is being refreshed, and the video signal is not in Vblanking region 28.
Video information is often interlaced, which means that during the refreshing of a field, only every other line on a video display device is refreshed. Two fields of video data are therefore needed to completely refresh the screen of a video display device. For example, FIG. 3 illustrates one method of interlacing using the NTSC format and a conventional picture tube embodiment of a video display device which focuses a beam to excite phosphors R, G and B and produce a color for each pixel. In FIG. 3, after a first Vblalnking followed by an Hsync 14 is received, Hactive 32 is asserted and line 1 is refreshed. Line 1 concludes with Hsync 14 followed by Hblanking 38, during which time the beam moves to the beginning of line 3. Hactive 32 is again asserted, and line 3 is then refreshed. This process continues for lines 5, 7, 9, etc. (the xe2x80x9coddxe2x80x9d field). After 262.5 lines of the odd field are refreshed, a Vsync 20 will be received with the first serration pulse occurring in the middle of a line rather than at the beginning of the line (the last half line of the odd field), signifying the end of the odd field. A Vblanking period 28 is then entered, during which time the beam returns to the top of the video display device. When an Hsync 14 signifying the start of the next active line is received, lines 0, 2, 4, 6, etc. (the xe2x80x9cevenxe2x80x9d field) are refreshed. When all 262.5 lines of the even field have been written, the bottom of the video display device is again reached, and a Vsync is received in alignment with an Hsync, which causes the beam to move back to the top of the display device and reset to line 1. The complete refreshing of a full screen of a video display device, including an odd field and an even field, is defined as one xe2x80x9cframe.xe2x80x9d
Because overlaying graphics information onto a video signal is often more easily accomplished in the digital domain, in conventional multi-media systems the analog video signal is first communicated to a video decoder which converts the analog video signal to digital information. The digital outputs of the video decoder are then communicated to a video encoder, where the pixel data is integrated with the graphics information and converted back into analog form to be compatible with typical video display devices. However, because the video encoder is asynchronous with respect to the video decoder, timing problems may occur during the simultaneous operation of the video decoder and the video encoder. Several techniques are known in the art for addressing this problem.
In the simplest approach illustrated in FIG. 4, a video decoder 40 uses a video decoder sampling clock to sample the analog video signal, and writes the sampled data into a frame buffer 42 (memory capable of storing an entire frame of video) using a write clock at a location identified by a write pointer. A video encoder 44 then uses a read clock which is asynchronous to the write clock to read this data out of the frame buffer at a location identified by a read pointer. There are disadvantages to this approach because the write and read clocks of video decoder 40 and video encoder 44 are asynchronous, and therefore their timebases will eventually drift apart. Eventually, when the accumulated drift of the timing difference between video decoder 40 and video encoder 44 reaches one frame, the read and write pointers in frame buffer 42 will cross. When this occurs, a frame""s worth of data will either be dropped or repeated. If this occurs within a field, rather than between fields, then a visible artifact is produced which is call a xe2x80x9ctear.xe2x80x9d
An additional field can be added to the frame buffer to eliminate the occurrence of tearing in the middle of a field (wherein the first portion of the field would contain data from one frame and the latter portion of the field would contain data from another frame). If a three-field buffer is used, the read and write pointers can be monitored to determine the field in which a crossing of read and write pointers will occur. Before the crossing occurs, however, the pointer that is about to xe2x80x9covertakexe2x80x9d the other pointer is moved xe2x80x9cbackxe2x80x9d in the three-field buffer by two fields (the three-field buffer being constructed in a recirculating manner). For example, if the buffer contains fields 1, 2, and 3, and it is determined that the read pointer will overtake the write pointer in field 3, then the read pointer is reset to field 1. This resetting of the read pointer will result in the repeating of one frame""s worth of data, but the timing of the reset can be selected such that it occurs in the Vblanking region of a field, when it will not produce a tear visible on the display device. For example, in consecutive fields A, B, C and D, without the three-field buffer a tear may occur in the active region of a field, resulting in a six-field sequence of field A, field B, a torn field C, a repeated field B, then field C and field D. With the three-field buffer, the reset can be manipulated to occur xe2x80x9coff-screen,xe2x80x9d resulting in a six-field sequence of field A, field B, an off-screen reset, a repeated field A and field B, then field C and field D. Visually, tearing is generally a more objectionable artifact than repeating or dropping a frame. This frame buffer solution is simple but expensive, for a frame""s worth of memory is costly.
A second approach is illustrated in FIG. 5. In this approach video decoder 40 includes a video decoder sampling clock 92 that is tightly line-locked to incoming analog video signal 46. A phase-locked-loop (PLL) and a loop filter within video decoder 40 detects where Hsyncs or subcarrier burst edges occur relative to edges of video decoder sampling clock 92 and continuously adjusts the frequency of video decoder sampling clock 92 to align the clock with the Hsyncs or subcarrier burst edges of incoming analog video signal 46.
However, these frequency adjustments to video decoder sample clock 92 may be significant when certain analog video signal sources are employed. In particular, VCRs are unstable video sources that do not generate consistent Hsyncs. The time between consecutive Hsyncs may vary by xc2x12 to 4 pixels per line, and thus the PLL may have to make a large adjustment to the video decoder sampling clock frequency to align the clock with the incoming analog video signal 46. Additionally, in VCRs a head switch line is encountered at the bottom of each field, which is substantially different in length from the other lines in the field. Although most lines will average slightly different than the ideal time of a line (e.g. 20 nanoseconds less), the error in the head switch line will be approximately equal to the accumulation of the error in all the previous lines in that field and opposite in sign. When a head switch line is encountered in the sequence of Hsyncs being tracked, a very large adjustment to the video decoder sampling clock frequency is necessary to achieve proper realignment by the time the Vblanking region is completed and the first few active lines in the new field are displayed.
The head switch line in VCR video sources is a product of the mechanics of a VCR. As illustrated in FIG. 6, a VCR includes a video head drum 102 with two playback heads 104 located on opposite sides of video head drum 102. As illustrated in FIG. 7, tape 106 is helically wrapped around video head drum 102. Tape 106 travels in the direction indicated by reference character 108, while video head drum 102 rotates in the same direction as indicated by reference character 110. Tape 106 makes contact with about 180xc2x0 of video head drum 102 at any time, and thus one playback head 104 is always in contact with tape 106. As video head drum 102 rotates 180xc2x0, one playback head will scan one field as it contacts tape 106, tracing a diagonal video track 112 across tape 106 as illustrated in FIG. 8. As video head drum 102 continues to rotate, the playback head will lose contact with tape 106, but the next playback head will be in position to contact tape 106 and scan the next field. In combination with the movement of tape 106 in direction 108, another diagonal video track 112 will be traced on tape 106 adjacent to the previous track. When the VCR switches from one head to another, the head switch line is created. In addition to the diagonal video tracks 112, diagonal Vsync tracks 114 and a longitudinal control track 116 on tape 106 are read by separate heads. The VCR uses this information to control the revolution rate of video head drum 102 and the tape speed to keep the field rate relatively stable and accurate.
Large adjustments to the frequency of video decoder sampling clock 92 due to a head switch line or other timing anomaly create difficulties in the video encoder""s re-creation of the reference subcarrier. Video encoder 44 receives video decoder sampling clock 92 and uses a known relationship between video decoder sampling clock 92 and the reference subcarrier to re-create the reference subcarrier. Typically, for NTSC analog video signals, the reference subcarrier must be 3.579545 MHzxc2x110 Hz (less than three parts per million (ppm)). However, to track the head switch line, the video decoder sampling clock frequency must be pulled many thousands of ppm away from nominal, changing the phase relationship between video decoder sampling clock 92 and the reference subcarrier. If this change in the phase relationship is not taken into account, the reference subcarrier re-created by video encoder 44 will be off frequency, and errors in chrominance processing may result. Thus, referring again to FIG. 5, information 48 indicating the extent of the frequency variation for a given line must be passed from video decoder 40 to video encoder 44 to properly re-create the reference subcarrier in video encoder 44.
In addition, when analog video signal 46 is from a source such as a VCR, the reference subcarrier is not mathematically linked to the Hsyncs, (i.e. the relative phase does not change by the same amount from line to line), and thus the phase relationship of the reference subcarrier and Hsync will not be consistent from line to line. The analog video signal communicated by video encoder 44 to the display device, including Hsync and a re-created reference subcarrier, will therefore have the same timing irregularities and reference subcarrier phase drift relative to the Hsync that exist in the source signal. Without a mathematically linked subcarrier, comb filtering and Y/C separation by the display device cannot be optimal.
It should be noted that the preceding discussion of the difficulties in tracking encoder read timing to decoder write timing illustrates a specific example of the more general problem of tracking the timing of asynchronous systems in a manner that accommodates timing irregularities in the reference system while maintaining a stable output in the tracking system.
Therefore, it is an advantage of embodiments of the present invention to provide a system and process for tracking the timing of asynchronous systems in a manner that accommodates timing irregularities in the reference system while maintaining a stable output in the tracking system.
It is a further advantage of embodiments of the present invention to provide a video signal processing system and process for tracking the read timing of a video encoder to a video decoder""s data stream to minimize the buffer size and to avoid dropping and/or repeating frames.
It is a further advantage of embodiments of the present invention to provide a video signal processing system and process with a reference subcarrier xe2x80x9cmathematically linkedxe2x80x9d to Hsyncs to optimize the performance of comb-filtered Y/C separation in a video display device.
It is a further advantage of embodiments of the present invention to provide a video signal processing system and process for receiving and tracking an analog video signal that makes only very small changes in the clock frequency of the video encoder and therefore minimizes subcarrier jitter or frequency variations that would generate objectionable hue errors in the video display device.
It is a further advantage of embodiments of the present invention to provide a video signal processing system and process for receiving and tracking an analog video signal that can synchronize to a newly changed source (e.g. a channel change) quickly enough that the total source change to video display device synchronization time is not onerous to the user.
These and other advantages are accomplished according to a method for adjusting timing of a secondary system with respect to a reference system. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference.
In preferred embodiments, the above-identified advantages and other advantages are accomplished according to methods for adjusting the read timing associated with reading data from sequential memory with a read clock, with respect to the write timing associated with writing data into the sequential memory with a write clock.
The post-synchronization tracking method decreases the read clock frequency if the amount of unread data stored in the sequential memory at the start of reading a new line of data has decreased below a predefined threshold over one field of data, and increases the read clock frequency if the amount of unread data stored in the sequential memory at the start of reading a new line of data has increased above a predefined threshold over one field of data.
The semi-accelerated frequency tracking method decreases the read clock frequency if an accumulated frequency drift is greater than a positive drift threshold, and increases the read clock frequency if the accumulated frequency drift is less than a negative drift threshold.
The accelerated frequency tracking method decreases the read clock frequency according to a schedule of negative frequency adjustments computed from the accumulated frequency drift and a gain factor if an underflow condition occurs in the sequential memory, and increases the read clock frequency according to a schedule of positive frequency adjustments computed from the accumulated frequency drift and the gain factor if an overflow condition occurs in the sequential memory.
The horizontal alignment method delays the reading of data from the sequential memory by a first amount of time if an underflow condition occurs in the sequential memory, and moves forward the reading of data from the sequential memory by a second amount of time if an overflow condition occurs in the sequential memory.
The vertical alignment method maintains a read line count for keeping track of how many lines of data have been read within a particular field, and determines a field misalignment value representing the timing difference between the start of writing a first line of data in a first write field and the start of reading a first line of data in a first read field. The method moves forward the reading of data from the sequential memory by an amount of time equivalent to the field misalignment value when the read line count in a second read field immediately following the first read field reaches a read line count adjustment point, if the sum of the field misalignment value and the read line count adjustment point is less than one field.